A team from Google Brain recently published a paper (on arXiv) describing the use of a Deep Reinforcement Learning algorithm to design chips customized for AI applications.  In other words, they used an AI to build AI chips.  The problem they faced was “placement of TensorFlow graphs onto hardware devices to minimize training or inference time, or placement of an ASIC or FPGA netlist onto a grid to optimize for power, performance, and
area”.  They note in the paper that Deep RL is well-suited to problems like this, “where exhaustive or hueristic-based methods cannot scale”.  The specific Deep RL family of algorithms they used were policy-gradient methods, such as REINFORCE, Proximal Policy Optimization (PPO), and Soft Actor Critic (SAC).   Using these techniques, the authors state their belief that “it is AI itself that will provide the means to shorten the chip design cycle, creating a symbiotic relationship between hardware and AI, with each fueling advances in the other”.